1. Technical Field
The present invention relates generally to manufacturing a semiconductor device, and more specifically to a contact hole structure of a semiconductor device and a method of forming the same.
2. Description of the Related Art
Semiconductor devices are manufactured through repeated procedures of depositing and etching desired conductive layers and insulative layers. For example, a transistor having source/drain regions and a gate line is formed in a silicon substrate, an interlayer insulative film is covered thereon, and then a metallic wiring is formed. In this process, since the transistor and the metallic wiring formed thereon are separated from each other by the interlayer insulative film, a contact hole is formed in the interlayer insulative film and filled with a conductive material, thereby providing an electrical connection passageway.
FIGS. 1A and 1B are sectional views showing a contact hole structure of a semiconductor device and a manufacturing method of the same according to the prior art.
Referring to FIG. 1A, a gate oxide layer 11 and a gate line 12 are formed on a desired area of a silicon substrate 10 and then a low-concentration region of source/drain region 13 is formed in silicon substrate 10. Then, a sidewall spacer 14 is formed at both sides of gate line 12, and a high-concentration region of source/drain region 13 is formed in silicon substrate 10. Then, an etch stopper layer 15 is deposited to cover the entire silicon substrate 10, and an interlayer dielectric layer 16 is deposited thereon.
Next, as shown in FIG. 1B, desired portions of interlayer dielectric layer 16 and etch stopper layer 15 are etched to form contact holes 17a and 17b. Contact holes 17a and 17b serve as passageways for connecting source/drain region 13 and gate line 12 to a metallic wiring, which will subsequently be formed. The contact holes are formed simultaneously above gate line 12 and source/drain region 13. The formation of contact holes 17a and 17b comprises the steps of etching interlayer dielectric layer 16 and etch stopper layer 15. Dielectric layer 16 may be made of an oxide, and etch stopper layer 15 may be made of a nitride.
FIG. 1B shows an ideal structure of contact holes 17a and 17b. In practice, however, since two contact holes 17a and 17b are simultaneously formed at two different areas, unexpected defects often produced. FIG. 2 is a sectional view showing an example of defects occurring in the conventional contact hole structure and its manufacturing technology.
Referring to FIG. 2, contact hole 17a formed above gate line 12 has a relatively shallow etching depth, dependent on the thickness of gate line 12. Therefore, if etch stopper layer 15 does not have a high etch selectivity, then over-etching is difficult to avoid when etching interlayer dielectric layer 16 to form contact hole 17a above gate line 12. As indicated by numeral 18 in FIG. 2, a defective gate line having a damaged upper end portion is formed, leading to a change in the characteristics of the semiconductor device, lowering reliability and yield.